The present invention relates to an abrasive composition for polishing a semiconductor device, more specifically, to an abrasive composition for use in element isolation of a semiconductor device by the shallow trench isolation process, as well as a process for manufacturing a semiconductor device using said abrasive composition.
As a method for isolating elements of a semiconductor device, a great deal of attention is shifting from the LOCOS (Local Oxidation of Silicon) process toward a shallow trench isolation process where a silicon nitride layer is formed on a silicon substrate, shallow trenches are formed and oxide layer is deposited thereon and then planarized by the CMP technique using the silicon nitride layer as a stopper, as the effective element region is wide and higher density semiconductor device can be fabricated.
In many of the shallow trench isolation processes, a silicon nitride layer is formed as lower layer of the oxide layer to be polished, the silicon nitride layer is used as the stopper in the polishing, the surface to be planarized is polished to give uniform and exact removed thickness, and the polishing is finished when a predetermined thickness removed is reached.
As the abrasive composition used to this effect, JP-A-9-194823 describes a composition using silicon nitride, silicon carbide or graphite as the particulate abrasive and JP-A-9-208933 describes an abrasive composition comprising silicon nitride fine powder having added thereto an acid such as gluconic acid.
These abrasive compositions contain an abrasive having high hardness and certainly ensure a high polishing rate, however, they are disadvantageous in that many scratches are generated on the polished surface and give rise to reduction in the performance of the semiconductor device.
Furthermore, the above-described techniques are sufficient in the xe2x80x9cselectivity ratioxe2x80x9d which is value obtained by dividing the polishing rate for an oxide layer by the polishing rate for a silicon nitride layer and shows how easy the oxide layer, in many cases, silicon dioxide layer is polished as compared with the silicon nitride stopper layer. Thus, there is a need to increase the selectivity ratio.
The object of the present invention is to provide an abrasive composition for polishing a semiconductor device, which can overcome the above-described problems.
Another object of the present invention is to provide a semiconductor device, which have solved the above-described problems.
As a result of extensive investigations to solve those problems, the present inventors have found (1) an abrasive composition for polishing a semiconductor device in the shallow trench isolation process, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a xe2x80x94COOH group, a xe2x80x94COOMX group (wherein MX is an atom or functional group capable of displacing a H atom to form a salt), a xe2x80x94SO3H group and a xe2x80x94SO3MY group (wherein MY represents an atom or functional group capable of displacing a H atom to form a salt).
Preferably, by using the abrasive composition for manufacturing a semiconductor device of the present invention, (2) wherein the concentration-of cerium oxide in the abrasive composition is from 0.1 to 10 wt % and the amount of the water-soluble organic compound added, in terms of the weight ratio to the cerium oxide, is from 0.001 to 20, and (3) wherein when a silicon nitride layer and a silicon oxide layer separately formed on a silicon substrate by the CVD method are independently polished under the same conditions, the ratio of the polishing rate for the latter to that for the former is 10 or more, the scratches on the polished surface can be significantly reduced and the value of the selectivity ratio can significantly increase.
The present invention also provides a process for manufacturing a semiconductor device, comprising the steps of
forming a silicon nitride layer on a semiconductor substrate,
selectively removing a portion of said silicon nitride layer to expose said semiconductor substrate,
etching said semiconductor substrate using said silicon nitride layer as a mask to form a trench,
depositing a silicon oxide layer on said silicon nitride layer and said semiconductor substrate to completely fill said trench with the silicon oxide layer, and
planarization-polishing said silicon oxide layer using said silicon nitride layer as a stopper to selectively remain said silicon oxide in said trench,
wherein said planarization-polishing is performed by using an abrasive composition for polishing a semiconductor device, said composition mainly comprising water, cerium oxide powder and one or more water-soluble organic compound having at least one of a xe2x80x94COOH group, xe2x80x94COOMx group (wherein Mx is an atom or functional group capable of replacing a H atom to form a salt), a xe2x80x94SO3H group or a xe2x80x94SO3My group (wherein My is an atom or functional group capable of replacing a H atom to form a salt).
In this process, shallow trench isolation can be formed with reduced scratches on the polished surface and with a high controllability.